Performance Analysis of Dual Tail Comparator for Low Power Applications

The dynamic regenerative comparators are used in analog to digital converters to reduce the power consumption, area and to increase the speed so it is necessary to design low power dynamic comparator for designing low power ADC. In this project, an analysis on the delay of the dynamic comparators is presented. From the analysis, an intuition about the main contributors to the comparator delay and the tradeoffs in dynamic comparator design are found. Based on that analysis, a new dynamic comparator is proposed, where the circuit of an existing double tail comparator is modified for low-power and fast operation even in small supply voltages. Without complicating the design and by adding few transistors, the positive feedback during the regeneration is strengthened, which results in remarkably reduced delay time. Post-layout simulation results in a 0.18-μm CMOS technology confirm the analysis results. It is shown that in the proposed dynamic comparator both the power consumption and delay time are significantly reduced. Keywords— Double-tail comparator; dynamic clocked comparator; high-speed analog-to-digital converters (ADCs); low-power analog design